After hours running various tests to determine when the voltage samples should be taken I concluded there was no right answer. Mind you, the sweet joy of using Forth to do this via the serial port was a reward in itself. ( Timing loops could be tested interactively, results displayed on the terminal window, etc etc. )

I settled on a longer delay before sampling the loaded voltage, or Vend in the code, then a short delay before sampling the unloaded voltage, or Vbeg in the  code. Because of the way the voltage depresses over time, then recovers, I doubt there is a right way to do this. But my training in Statistical Process Control and Gauge Capability steered me in this direction.

I now have a testing method that gives me repeatable readings provided each test is run hours apart. So while the calculated internal resistance might not be the value according to some standard it should allow me to discern if my pulse conditioning circuit has any impact over time on the internal resistance.

Over the next few weeks I'll run my trials and see what happens.