I'm happy with the basic design of the programmer hardware and firmware.  It's really cheap and tiny and that was the goal.  There are a few revisions I would like to make however:

• Additional staggered JTAG through-hole header.  The JTAG header was designed with staggered holes so that it can be used naked like a socket.  However, I discovered some pin headers are thinner than others.  Because of this I want to add an additional through-hole JTAG header with more aggressive offsets to use on these thinner pins.
• Surface mount JTAG header footprint.  It would be nice to have the option to use a right-angle surface mount female socket for the JTAG connector.  This would allow for that.
• Power and status LEDs?  These are common...but I'm considering assembling a lot of programmers by hand.  The fewer components I have to add the easier it is for me to assemble.  At least I can add the footprints.
• 3.3 volt and ground access.  A couple of through-holes for power and ground could be useful if you want to power your FPGA board from the programmer.

These changes will be pretty easy, but they are not the next task to tackle.  Instead I need to focus on the code used to talk to the programmer.  The programmer hardware itself is more like a USB-GPIO device than anything else.  The python code talking to the programmer will implement the JTAG protocol and FPGA programming sequences.  This is what I need to implement now.  The first plan is to implement an SVF JTAG player that will read SVF files generated by the Lattice tools and use them to program and test the FPGAs.  Once I have that I should be able to figure out the commands and sequences to program the FPGA over JTAG.

Stay tuned here and the project GitHub page for updates.