Preliminary specifications for the new design (subject to change):

1) 12-bit word size

2) single accumulator

3) will have carry bit (register)

4) 4K words of RAM

5) paged & indirect memory access

6) 4 "indirect" registers

7) RS-232 I/O @ 150, 300, 1200, 2400, 4800, 9600, 19200, 38400 bps

8) microcoded

9) up to 4K micro instructions

10) 24-bit micro instruction word size

11) real front panel w/switched & lights (LEDs)

12) 5V only operation

13) target system clock speed: 5MHz

14) implemented w/mostly 74F series logic (because that's what's most easily available)

(1), (2) & (8) are required for it to remain STUPID.  The control logic doesn't care about word size, so it could just as easily be a 16, 18 or 32-bit CPU.

Most of the rest of the features listed above are to eliminate the limitations in the original design (see Overview video).