I sent the gerbers and associated files to PCBWay for manufacture and assembly.  The BGA package on the ECP5 FPGA I'm using requires 0.15mm via drills and 4 copper layers to route out all the necessary IOs, grounds, and power rails.  This means it's an advanced PCB process that has much more expensive fixed costs.  I've reviewed the board layout and schematic several times.  It should work.  I think.  It will be very interesting to see what sort of issues pop up.  When I do get the prototypes back in a month (if I'm lucky it will be that fast!), I'll have the following things to checkout in roughly this order:

• 3.3v switching regulator
• 1.1v switching regulator
• 2.5v LDO regulator
• 1.8v LDO regulator
• FPGA JTAG
  • I should be able to hook it up to the lattice programming cable and get some signs of life
• SPI Flash
  • I should be able to read and write the SPI flash using the testpoints
• FPGA/flash connection
  • I should be able to make a simple LED blinky design to make sure the FPGA can read its configuration from flash.
• 16MHz MEMs clock
  • I should be able to make a design using the 16MHz clock and it should work
• USB Bootloader
  • I'll be porting the #TinyFPGA B-Series USB bootloader to the ECP5 FPGA.  I've included a dynamic pull-up resistor on the USB lines so I can make the connect process more reliable.
• HyperRAM!
  • I'm super excited about the HyperRAM...but it will be a new challenge to develop a robust interface for the HyperRAM since it uses a unique DDR protocol called HyperBus.

There's plenty of work to do while I'm waiting for the boards.  Beyond getting ready for the initial checkout of the prototype boards, I'll also be designing a pogo-pin test bed for production checkout of all TinyFPGA E-series boards.  The pogo pins will contact each of the IOs as well as all of the power rails and test points on the bottom of the board to access the SD Card interface, JTAG, SPI, PROGRAMN, 1.1v, 1.8v, and 2.5v nets.