I’ve done a fairly significant amount of digital design with VHDL. Some of VHDL’s drawbacks include a type system that can be confusing for beginners, as well as verbose syntax and a lack of case-sensitivity. Some of my projects became difficult for me to manage because of the verbosity, so I decided to look for alternatives. I didn’t really find anything that looked like it would solve my problems without creating a lot of new ones. I decided that making a new hardware description language heavily based off of VHDL would be both a great learning experience as well as an opportunity to make a tool that would help me and potentially others.