The Ternac2's instruction set is rather sparse at a mere 20 instructions and 4 registers. I ultimately plan to build this machine and with the lack of off the shelf ternary ICs I'm expecting to need a lot of discrete components. This means the machine's underlying hardware has to be kept as simple as possible. I think I've come up with a good compromise.
The machine itself has two working registers, the Accumulator and the Operand register. All results from the ALU and Memory units will be stored in the Accumulator. The operand register is intended to be the second operand for any ALU operations needing two inputs. To make the hardware simple the operand register will only be accessible by swapping with the A register. In hardware we'll just rename the two instead of actually moving bits.
The architecture also has two other registers important for higher level languages: A stack pointer and an Index pointer. At 12 trits each these registers will be expensive but I think they will greatly simplify the task of programming. The stack register is necessary for procedural languages, while the index register makes operating on arrays and structures easier.
The final instruction set is below:
Mnmonic | Name | Operation |
Arithmetic And Logic | ||
ZAC | Zero Accumulator | 0 -> A |
NAC | Negate Accumulator | -A -> A |
AAC | And Accumulator | A & B -> A |
OAC | Or Accumulator | A | B -> A |
XAC | XOR Accumulator | A XOR B -> A |
ADD | Add Accumulator | A + B -> A |
SUB | Subtract Accumulator | A + (-B) -> A |
Branch and Test | ||
JAF | Jump Flags (Indirect) | if (op1 & flag) then (PC + 2 + op2) -> PC |
JIX | Jump Index Register | IX -> PC |
Load and Store | ||
PSH | PUSH | A -> [SP++] |
POP | POP | A -> [--SP] |
LSL | Load Stack Low | A -> SP[0] |
LSH | Load Stack High | A -> SP[1] |
SIL | Swap Index Low | IX[0] <-> A |
SIH | Swap Index High | IX[1] <-> A |
SWP | Swap | A <-> B |
LIM | Load Immediate | op1 -> A |
LIA | Load Indirect A | [IX] -> A |
IO | ||
OUT | Output to terminal | A -> Term Device |
IN | Input from terminal | Term Device -> A |
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