Arduino-Compatible FPGA Shield

Had some fun tonight playing around with PCB routing.  You can see in the PDF in git or the PCB file (you'll need altium to open it) that I'm all about "pretty".  :)  Still a fair bit to finalize the routing and design and such but moving along nicely.  If only I could stretch the day to 27 hours!

Uploaded video number 4 to Youtube, showing both SPI Multiplexing with a TI Bus Switch, and also implementing Asychronous SRAM (128K x 16).  Next up, power supply! 

Made a number of little tweaks this weekend and uploaded a new SRAM document, new SPI multiplexer doc, made tweaks to the top level to integrate these elements and just finalizing some bits here and there.  Complete details in github.  See link in project links.  :)

Uploaded  video no. 3 explaining the schematic overhaul, JTAG wiring (w/ a little background on JTAG - though focused on the implementation), and discussing the decoupling.  For a detailed discussion of JTAG, I suggest having a look at EEVBlog and Dave Jones' video on JTAG and Boundary Scan.  He does a great job explaining the in's and out's for the novice and the old pro alike.  

I have also uploaded detailed schematics to my repository in git.  

Next video we'll discuss the SPI multiplexing (necessary if the FPGA and Arduino are both going to master the SPI flash) and the power supply.  Also finalizing the IO and finally we'll move into layout.  Parts have been ordered and arrived today so it is moving along quickly!

Updated the schematic over the weekend to clean up the wiring and group signals, sheets, etc. more intelligently.  A new version of the source files and a PDF can be found on the git repository.  A direct link to download the PDF can be found here.   I will also be going thru and adding better labels on schematic to make everything more readable and finally completing the final bits of IO routing and the power supply.  All should be wrapped up this week (hopefully).

As always, comments, suggestions, noted errors, etc. are all welcome.  This is still very much a work in progress but getting close.  Should also note that I ordered prototype quantities and anyone interested in testing should let me know via the comments of pm me.  

Uploaded a heap of stuff to git.  Working on video now.  This includes two layers of top level documents that show sheet to sheet connectivity between SPI and the FPGA and also have the breakout for the FPGA IO and other various items.  Added a new PCB PDF that shows the board file with this breakout schema.  Eager to get feedback on this approach to breakout and also the schematic structure. 

Video to follow.

​FPGA decoupling can be tricky to sort out without some guidance.  Thankfully, Xilinx provides a pretty comprehensive PCB Layout guide that has specific recommendations for decoupling schemas for the PCB, based on specific parts and pin counts.  I have followed these and attached a reference to the document in the list of related links alongside my project.  I will add this to a video (to follow) that describes exactly how this all fits together.

For details on the recommended decoupling caps for this family, refer to page 14 of the ​PCB Pin Planning Guide for the Spartan-6 family.  I am using the TQ-144, LX9 (as of this writing, pg. 14, second row).  Please post questions, concerns, etc in the comments and I'll do my best to answer them.

Files uploaded to git.  FPGA schematic updated also to reflect decoupling child sheet.

​Uploaded files to my git repository with the JTAG wiring completed.  Video to follow.  The basics are pretty straight forward:

- Broke out JTAG signals

- Add pullups to ensure JTAG is always in a known state

- Add terminations 

- Generate bus port (signal harness) to take signals off-sheet (seen later in the top level diagram to follow)

PDF and schematic source files are in git and available for download.  

​I've uploaded the SPI Flash schematic to ​git.  I'll do a video discussing this schematic & the connections between the Flash and the FPGA device @ the top level and how that ties into the backend Arduino and any other top-end boards you might want to connect up.

​Completed the first part of the FPGA wiring for Master Serial / SPI mode - i.e. configuring the FPGA from SPI flash.  Created a video that details some of the nuances and aims to explain the wiring in the schematic a bit.  Files uploaded to git and the video is available below: