So, the results are different than expected, but that is just fine. I'm running my V200 at 2x the speed it came from TI. For those who are TL:DR with my logs, you need a 1.21 kOhm resistor and an 18 pF capacitor. I never ran the MD5 checksums as I didn't see anything that presented as instability and I had a continuity problem in a wire from the battery pack that I couldn't be bothered to fix and taking that extra step was too tedious. That at sending a new OS file took about 3.5 min and I had to repeat this test at least once on each over clock after waiting for everything to cool down because even the contrast of the screen was affected by the hot air rework. Results posted after the break.

Okay, so in the course of benchmarking I quickly began to further understand the timings a bit better for the SRAM. The pulses for CE and WE are the crucial ones that are the determining factors for read and write time in this case and I only recorded these values for the 2 highest overclocks. In order of slowest to fastest, here are the results of today's tests:

1.43 kOhm & 51 pF - Stock

• 12.7 MHz RC clock @ 15.2 dB
• 13.6MHz MK68K clock
• NOR ROM Access speed: 1.8 MHz

1.43 kOhm HQ & 33 pF - ~30% OC

• 16.55 MHz RC clock @ 15.6 dB
• 18 MHz MC68K clock
• NOR ROM Access speed: 2.25 MHz

1.43 kOhm HQ & 24 pF - ~55% OC (forgot to grab screen shots)

• 19.4 MHz RC clock @ -- dB
• 21.46 MHz MC68K clock
• NOR ROM Access speed: 2.65 MHz

1.43 kOhm HQ & 18 pF - ~80 OC

• 22.1 MHz RC clock @ 13.6 dB
• 24.87 MHz MC68K clock
• NOR ROM Access speed: 3.1 MHz
• WE time: 38 ns - spec is >35
• CE time: 57 ns - spec is >45

At this point its apparent that the rise and fall times are becoming a bit lengthy relative to the periods. Just to see what would happen, I opted to drop in the 1.21 kOhm resistor of similar spec to see what effect it would have. As it would speed up the RC oscillator, I dropped back to 24 pF...

1.21 kOhm HQ & 24 pF - ~75% OC

• 21.6 MHz RC clock @ 13.6 dB
• 23.84 MHz MC68K clock

So, for about a 4% loss in speed, I gained ~5% faster rise and fall times. Rounding error could attribute for the difference since the numbers computer were of the screen values, not the sampled points with how Rigol doesn't their math.

1.21 kOhm HQ & 18 pF - ~100% OC

• 24.7 RC clock @ 13.6 dB
• 27.55 MHz MC68K clock
• NOR ROM Access speed: 3.45 MHz
• WE time: 34.4 ns - spec is >35
• CE time: 51.6 ns - spec is >45

Tonight's notes:

• The resistor directly affects the rise/fall times of the MCU/CPU clock
• NOR Flash still has room to be "overclocked" though the datasheet implicitly specifies a 5 MHz speed.
• SRAM, even the faster stuff I put in, is technically at it's limit for the overclock.
• Output frequencies do not align with a simple account of parasitic capacitance addition. In the morning I'll plot the data and see what's happening if I can.
• The only game I crashed was SD II, but it was in the same manner both times and given that I've played it before, this came across as a software bug, not a result of the overclock.
• I timed link transfer speeds by nature of sending the OS over. Every results except for stock and the fastest were 3 min and 25 seconds. Stock was 3 min, 40 sec, and 100% OC was 3 min, 50 sec.
  • Since the back half of my TI-89 is soldered to my V200 for power, I could not test calculator-to-calculator speeds.
• Especially after dropping the resistor's value, the screen of the calculator dimmed its contrast a noticeable amount when the CPU was engaged. This is common in low battery situations and it seems that the LDOs next to the ASIC are partly responsible for powering the LCD drivers.
  • This and temperature sensitive contrast is something I wish to investigate and minimize if possible.