Sadly, DFF (the normal gate that samples the input data when the clock rises) are silicon hogs. It will depend on your PDK and SCL of course but one DFF is two transparent latches (unless you use the Earle topology, which has been abandoned).

These DFF gates are essential and need to be used all over the place but many circuits do not require them, yet your HDL coding habits will lure you into implementing more and more. For example certain control/configuration registers, IO ports, and even the register set can be shrunk (which also draws less static power and saves silicon real estate)

Of course if you play with FPGA, the DFF are "free" and this won't make a difference, until you port to ASIC and your floorplan with explode: what was free now costs 4× or 6× more than a normal boolean gate.

4-phase clocking can be used for long pipelines (multipliers ?), if the circuit can be cut into 4 equal-time slices.

And this applies to "standard CMOS", as Domino logic rewrites all the rules (but you're unlikely to encounter this unless you work for the biggest companies)