Yann Guidon / YGDESSeveral processors start execution at more or less arbitrary addresses. There is actually a large variety of approaches and implementations. This was mostly driven in the early (golden age of) microprocessors by the need to have separate RAM and ROM address ranges. Some had a "fast page mode" that favors the first 256 bytes of memory so it was impossible to put ROM at the lower addresses.
The Intel 8088/8086 would boot to FFFFEh (mapped to BIOS EPROM) and locate the IRQ table at 00000h (in DRAM). But the reset vector is also sometimes one entry in the "interrupt vector table" (see the 6809). Should it be in ROM or RAM ? If it's in ROM, you can boot but you can't modify or reallocate the vectors to user code. See the last log Interrupt vector table
Anyway, many current processors boot from a serial EEPROM. Some circuits load the contents of the EEPROM into main RAM or in the cache, so the problem of the overlap of RAM and ROM is now a thing of the past.
Booting at address 0 is easy and future-safe (just look at the x86 and the extension of its address space...)
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You're confusing terminology here. "Fast page mode" usually refers to the ability of DRAM to perform many CAS cycles without needing a RAS cycle between them, thus improving performance over systems where every access needed both RAS and CAS. The concept you're talking about here was usually called either "zero page" or "direct addressing", and was used on the 6800, 6502, and I believe the TMS9900. Another related point is that the stack pointer in the 6502 was also hardwired to start at a particular address and wasn't easily modified, so as well as 256 bytes of RAM at 0000h you generally needed another 256 at 0100h for the stack. Machines with less than 512 bytes (I'm looking at you, Atari 2600) made multiple copies of their RAM in these ranges to let both stack and zero page coexist.
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More precisely, the 80x86 processor family boots at {,E,R}IP=0000h, and it's the *code segment* base address which is set to -1. This means that the first instruction fetched by x86 CPUs is at address 0FFF...FFF0h.
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