Now that the prototypes of the GPS disciplined oscillator has proven to be a success, I've made up the final solution to the crazy clock calibration.

It's more or less the same solution as before - an ATMega328p connected up to a 2x16 LCD as a "backpack." There's a 1.8 volt LDO to supply the clock board being tested with power, and the pin carrying the 16.384 kHz square wave from the calibration firmware goes into the ICP pin. Rather than an oscillator on the board, there's an 74LVC1G17 Schmitt trigger buffer chip that acts as a clock "reconstitution" chip. It's fed from a 3.3 volt LDO (so that its input voltage range is more compressed - a 3.3 volt logic output will successfully clock the controller). The input comes from a 50 ohm Thevenin terminator right after a DC blocking capacitor. That, in turn, is fed from a header that's connected via a cable to the GPSDO. This configuration should work not only with the 3.3 volt LVCMOS square wave from the GPSDO, but with a 1v P-P sine wave.

The firmware is the same as I was running before, but is set up for a 10 MHz clock rather than 20 MHz. That done, the special self-calibration mode of the firmware reports a 0.00 ppm error when it's hooked up to a GPS module. That's as you'd expect, of course, seeing as how that's just testing whether two otherwise identical GPS receivers can agree to within 10 ppb.

I've now already used this solution to calibrate clock controllers for a customer, so... yay!