I'm reviewing existing schematics again and making improvements and simplifications using Wired AND logic where appropriate. So far I've added an unbuffered version of the Min gate and I believe I can make a simplified version of the AntiMin gate as well but haven't tested it yet. Simplified versions of the Nonimplication, Converse Nonimplication, and XNOR gates may also be possible but it will require a little more thought and experimentation to verify those.

Here's the updated schematic showing the new unbuffered Min gate.