The equality gate outputs plus when both inputs are the same; otherwise it outputs minus. I initially thought to make this gate using a combination of two monadic 2's (+ - -), two 6's (- + -), and two K's (- - +). These could be arranged such that the gate always produces a - unless both inputs were the same. This would have required 8 comparators since 2's and K's are one comparator each and 6's use two comparators each. Instead, I worked out that, but judicious use of wired AND and wired OR I could build this gate using two P's (which can be implemented with just a couple of diodes), two A's (two comparators each), two 4's (one comparator each), and a single 2 gate (one more comparator). That comes to a total of only 7 comparators. Yay.
The P OR P gate is a Max gate
B | B | B | ||
- | 0 | + | ||
A | - | - | 0 | + |
A | 0 | 0 | 0 | + |
A | + | + | + | + |
The A OR A gate (The DAD gate by my naming convention) looks like this
B | B | B | ||
- | 0 | + | ||
A | - | 0 | 0 | 0 |
A | 0 | 0 | - | 0 |
A | + | 0 | 0 | 0 |
And the 4 OR 4 gate (DD4 gate) looks like this
B | B | B | ||
- | 0 | + | ||
A | - | 0 | 0 | 0 |
A | 0 | 0 | 0 | 0 |
A | + | 0 | 0 | - |
If you look at these three truth tables and just take the lowest value in each position (through the use of Wired AND) you get this truth table
B | B | B | ||
- | 0 | + | ||
A | - | - | 0 | 0 |
A | 0 | 0 | - | 0 |
A | + | 0 | 0 | - |
By passing this through a 2 gate (+ - -) the -'s get turned into +'s and the 0's get turned into -'s and you get this
B | B | B | ||
- | 0 | + | ||
A | - | + | - | - |
A | 0 | - | + | - |
A | + | - | - | + |
And thus we have a Equality gate. One that only returns a + when the two inputs are the same and returns a - otherwise. Here is the schematic.
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