I've leveled up my "rewrite this VHDL to optimize for pterms/macrocells/function block input" skills, and I think I've got the hardware working perfectly as of tonight. I had to remove some 'nice to have' stuff - double buffering my clock domain crossing for writes and resets being the biggest - but the version I've got up on Github as of a few minutes ago is about my maximal effort: https://github.com/dqydj/VGAtonic/tree/master/First_Draft/CPLD Firmware

I'm a software guy at heart... bring on the Microcontroller! Let's add UART input, shall we?

(Exactly how we're going to arbitrate that I'll write up a new post in a few minutes).