DIPSY

[christoph] I seem to love making blinky examples. My latest series of git commits cover the blinky basics, such as

• using open drain outputs for an LED with current limiting resistor,
• the built-in constant current LED driver (no resistor required),
• low-frequency oscillator (10 kHz) and
• high-frequency oscillator;
• dividing clocks down to something useful (visible)

While Lattice Diamond Programmer or DIPSY SPI Tool can be used on PC to write spi flash, Hackaday project #SPI Flasher May also offer direct SPI flash writing from Rasperri Pi

Thanks Yann!

I found some very old AT45DB161E SO8 and made "flash adapter" for the DIPSY-EasyPCB to test standalone boot from flash. Lattice Diamond did have this device in the Flash selection list, but was not able to write the flash.

So I did give a try to DIPSY SPI Tool what I did finish a few hours later - there was from old times some SPI functions included.

To my big surprise DIPSY SPI Tool, well it did write the flash, and voila:

dipsy has lots more resources than necessary for creating a WS2812B driver. On our way to a really useful implementation I created the actual driver core that converts 24 bits to the correctly timed pulse train and tested it with a single "pixel":

After hours of troubleshooting I decided to connect my logic analyzer - only to find out that I had connected the WS to the wrong pin. Well, that's life.

I also created a "cycling" example that cycles through red, green, blue and white over and over again. Both can be found in my git fork (/THP2015/examples/verilog/ws2812b_standalone), soo to be pulled into antti's repository.

The goal is to create a WS driver chip with a frame buffer and SPI interface. The dipsy FPGA has 14 RAM tiles with 512 bytes each, so we can easily drive a total of 2048 pixels (using 12 tiles: 4x512, 3 bytes for each pixel) with this thing.

This blog post was very helpful in understanding the timing: https://cpldcpu.wordpress.com/2014/01/14/light_ws2812-library-v2-0-part-i-understanding-the-ws2812/

It all depends on your view angle:

DIPSY in Barcelona!

And this is the ICON to be used in for DIPSY :)

The dipsy FPGA is intended to be used as an LED driver chip, but we can also use the LED pins (RGB0..2, IRLED and BARCODE) as user I/O. To do so, special driver IP needs to be used. Here's a simple verilog source to demonstrate this:

module top (
  input pin_in,
  output pin_out
);

wire mywire;

SB_IO_OD #(
  .PIN_TYPE(6'b000001),
  .NEG_TRIGGER(1'b0)
) pin_in_driver (
  .PACKAGEPIN(pin_in),
  .DIN0(mywire)
);

SB_IO_OD #(
  .PIN_TYPE(6'b011001),
  .NEG_TRIGGER(1'b0)
) pin_out_driver (
  .PACKAGEPIN(pin_out),
  .DOUT0(mywire)
);

endmodule

assign pin_out = pin_in;

SB_IO_OD #(             // IP name
  .PIN_TYPE(6'b000001), // configure as simple input, no output capabilities
  .NEG_TRIGGER(1'b0)    // don't know what that means exactly
) pin_in_driver (       // the instance name
  .PACKAGEPIN(pin_in),  // the pin to use as input
  .DIN0(mywire)         // where to put data from that pin
);

The output is very similar:

SB_IO_OD #(
  .PIN_TYPE(6'b011001), // configure as simple input pin
  .NEG_TRIGGER(1'b0)    
) pin_out_driver (
  .PACKAGEPIN(pin_out), // connect to output pin
  .DOUT0(mywire)        // with data from this wire
);

This example is currently in my own dipsy fork (THP2015/examples/verilog/basics/01_inout/), but I've already created a pull request for antti.

Two set of DIPSY + DIPSY EPT are on the way to Lattice I have received samples and free eval boards from Lattice, now there is something I can give back!

DIPSY so COOL with ICE COOL PFGA on it

Created an eagle library with two simple dipsy schematic symbols and footprints:

• one full version with all 14 pins,
• one breadboarding-like version with the 8 outer pins.

I couldn't really test it (yet), but I think it's ok as it is.

Find the library in the dipsy main github repo

It's very cool that xilinx give us free software (Vivado) that we can use to simulate our designs. BUT there are some gotchas. When I tried to simulate writing to/reading from RAM it seemed that nothing worked as intended, until I simulated for a longer time (> 100 ns). After skimming the datasheets, RAM usage guides, I finally opened the "Vivado Design Suite User Guide", where I found this:

"Apply stimulus data after 100ns to account for the default Global Set/Reset (GSR) pulse used in functional and timing-based simulation."

This boils down to: RTFM. Ah well...

Many years have passed since I last looked at Fritzing. Nice to see many improvements. Its is really a breeze to make simple stuff. Really.

This is all you need to load a DIPSY hardware "BITSTREAM" a 30KByte binary file using TEENSY.

Amazing, and it is instantly documented the hardware setup.

And you have schematic too!

And autorouted PCB also.

And there is no need to use screen capture, all views can be saved to bitmap files.