Vivado IP Catalog, click click.

Vivado IP Integrator, click click.

Xilinx SDK (Eclipse):

void SetWS28xx(u8 RED, u8 GREEN, u8 BLUE) { putfsl(RED << 16 | GREEN << 8 | BLUE, 1); }

    while (1) {
    	SetWS28xx(r, g, b); //
    	r++;  	g++;  b++;
    	MB_Sleep(10);
    };

Get 3 wires

Connect the wires

FAIL

Get Oscilloscope, power it on

Can not wait? Look at the wires again, SWAP ground and signal and

you will see

That WS2812 does work, and is controlled by software.

This is first time I ever used WS2812.

As soon as fixed the problem with the wiring, it just worked, namely:

1. CPU0 Bootrom did load FSBL into OCM ram
2. FSBL did load FPGA code that is the "HARDWARE" from an partition in the SPI Flash
3. This BITSTREAM was DMA'd into ZYNQ PL - Programmable logic
4. PLL in Processor part of ZYNQ was set to deliver clock to fabric side
5. In the Programmable Fabric an 32 Bit Soft core MicroBlaze is booting from Block RAM that was loaded together with the bitstream during the FSBL boot proccesses
6. Microblaze exectutes the main.c - code above
7. The c code uses special processor instruction that directly writes the data to streaming hardware port
8. This data is latched in WS2812 IP core
9. The IP core generates the timing
10. WS2812 is controlled by the software :)

You think this can not be true?

That this all just works first time tested?

Well then you would not believe I can do #HAD-9000 in 2016 either?

Without your help, I can not. With your help WE can.

Would you like to work on HAD-9000 ? You can.

You can start now with Soft-Propeller, its gives the boost you need to be ready for HAD-9000 in 2016.