One of the biggest limitations of the current design is the granularity of the phase discriminator. The current design counts the number of rising edges of the clock between adjacent rising edges of the PPS output of the GPS receiver. This system can only detect entire missing or extra cycles. In other words, its detection granularity is integral cycles. An error of 1 cycle out of 10 million is a granularity of 100 ppb. My methodology has been to average over 100 seconds to obtain 1 ppb of granularity, but it takes 100 seconds to do this.

Jim Harman of the Time Nuts mailing list has shared with me his design for a phase discriminator that offers a vast improvement - the ability to detect fractional cycle phase differences.

His design uses the phase discriminator section of a 4046N PLL. The design starts with a divide-by-ten prescale for the output of the oscillator. This gives a 1 MHz square wave for the PLL, whose maximum operating frequency is 2.4 MHz. This PLL actually has 3 different phase comparators in it, and Jim uses the third one. For every PPS pulse, the phase detector will output a pulse of between 0 and 1 µs - that is, the time between the rising edge of the PPS signal and the next rising edge of the 1 MHz clock. The intent is that the design will attempt to lock in a 180 degree phase difference - so that the two rising edges are 500 ns apart. Jim uses a Schottky diode feeding an RC circuit to convert the variable width pulses into a variable voltage. A second resistor across the filter discharges the cap over the course of the second. The PPS causes an ICP interrupt, which can be used to read an ADC to detect the captured voltage. The value obtained from the ADC can be scaled to add additional fractional bits to the integral phase difference detected by counting clock cycles.

This design is intriguing, but there are two immediate challenges that would need to be solved. First, the ATTiny4313 has no ADC. This means swapping it out for another AVR chip that has at least one UART, a 16 bit timer with ICP, an ADC and enough I/O pins for the job. The ATTiny841 is a good nominee. Further research is necessary. The second problem is finding space on the board for two more SOIC-16 chips - the LS390N decade divider and the 4046N PLL. The alternative to that is choosing a new enclosure - and throwing away all of the work that's been done on the current solution.