Antti Lukats
Clocks above 1 GHz are not yet possible in FPGA fabric, however implementing functions that run at 20GHz virtual clock is possible.
For the NCO design we would have to run all real calculations at some suitable for FPGA fabric clock speeds, staying say below 300mhz. At this sytem clock we calculate multiple NCO values and for each actual change of output adjust the DELAY.
Delay steps can be 78ps or 52 ps. When using 52 ps Delay tap size the NCO output signal time precison would be 52 ps what is equivalent to single NCO running at 20GHz.
Kevin H. Patterson
Tobias Rathje
Ken Yap
Mert