VGA side now works with 8-bit fetches from display RAM, and the design synthesises again! Also, fixed a timing issue with the Flash attribute where it flashed a character early, and added in the logic for extending box-graphics characters so they join up.

I also finally slowed down the Z80 clock enough that I could see A11 toggling away. Yay! Then I found that I can edit the contents of FPGA blockRAM (including ROMs, but not dual-port RAM) while the system is running, using the Quartus JTAG tools, so I was able to prove to myself that it's really fetching instructions from the ROM by moving the JP 0000 nearer and further from the end - A11 flashes faster, and not at all if you put the JP instruction in the lower 2K of ROM. So that's cool. I found the option to rebuild the bitstream with new memory images without changing the logic too (3 seconds vs 2 minutes), which will be helpful for the software side of things.

However, the 9 bytes of real code in the ROM was supposed to write a character to the display RAM, and that isn't happening. In fact, the synthesis tools seem to be optimising the 1K (other) RAM away altogether, so something isn't quite right there. I suspect it's with the address decoding logic (a funny mix of active-low Z80 signals and active-high signals for the IP memory), so it might be time to get the simulator going again, although with a full CPU in there it might take a while to run!

Next steps:

1. Writeable RAM
2. Figure out an OK development environment for writing Z80 assembly and/or C.
3. Get the UART hooked up to the outside world and prove that it reads/writes, too.
4. PS/2 interface is next, I guess.