VHDL vs Verilog

Going random:

it is of benefit to be able at least to understand both
in many cases it is possible to use them mixed in same design
verilog == c
VHDL == Pascal (Module)
if you use ICE FGAS, with verilog less hassle
ASIC world prefers verilog
FPGA world prefers VHDL
simulation testbenches are easier in verilog

There is no one winner.

Discussions

Dimitar Tomov wrote 09/02/2015 at 08:36

By the way I've been trying to understand with my preliminary knowledge for FPGA development why VHDL is preferred in designing glue logic and for high-level ASIC as LTE modems, etc.

To me Verilog makes more sense , not only because it resembles C and that's my mojo, but also in terms of clarity in Debugging. Including readability of the source <> maintaining the code.

Yet again I admit I have preliminary knowledge and very narrow experience with FPGA. Been eager to start for some time now. With DIPSY + New architecture in mind I've decided the postponing have been long enough ;)

Thanks in advance for the time :-) Looking forward to your answers.

Are you sure? yes | no

Yann Guidon / YGDES wrote 08/26/2015 at 20:51

VHDL diehard here ;-)

Are you sure? yes | no

FPGA use Example 2: glue logic replacement

Embedded Instruments

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