The big picture in IPI BD:

The audio block, is implemented based on IP compatible to Analog devices SPDIF IP Core, so we can reuse eixsting drivers. The IP Core has been modified to expose not SPDIF but AXI4-Stream as audio output interface, what is connectef to AXI4-Stream to PWM IP Core. Please note that this IP core is using Cortex A9 DMA channels, the DMA engine is not created in the FPGA.

HDMI Output is also rather simple, Xilinx Video DMA is used to to get framebuffer data from DDR memory, this video streami is converted to color format supported by Linux simple framebuffer drivers, and then it sent to HDMI serializer. VDMA init is done in the FSBL, also logo is loaded by first stage bootloader so it appeary very quickly during startup.

MIPI CSI2 camera processing path is bit longer, it is first converted from CSI2 signals into intermediate PPI Interface also defined by MIPI alliance as the MIPI PHY interface. PPI is then converted to AXI4-Stream. As next step the video data passes dual clock FIFO to move into system clock domain. Then the camera data is processed to convert RAW10 format into RGB. Before going to Xilinx VDMA IP Core the video data is resized so that it can directly be displayed on HDMI monitor.

Thats it folks.