As the P1A board progresses, the time is coming to implement the circuit studied in https://hackaday.io/project/8121-discrete-yasep/log/26931-asynchronous-serial-reception.

The design has two shortcomings : the incomplete validation of the start bit and the absence of an external reset. Upon power-up, the circuit might send spurious data. A third safeguard would be to block/stall the receiver if the stop bit is 0, until it returns to 1. This way, a dangling input will not be decoded as a stream of 0s...

So it's a 4-states finite state machine:

• [0] wait-receive / reset, CLR is 0 (counter not running, frozen to 0)
• [1] receiving start bit (should return to [0] if input is high before the condition is met) (CLR=1, running)
• [2] receiving data (CLR=1, running)
• [3] wait until input is 1 (fault condition, CLR=0 to prevent overflow)

This might be implemented as a 1-hot FSM using a '273 (running off the 3.6864MHz main clock) because it has a CLR input too, which can be controlled with a general active-low RESET signal. 5 of the '273's D-latches are used, 3 might be used for other purposes.

We can also play with the active level of each state. For example, [0]=0 is the reset state so it is active low. If we define [3] as active low too, but [1] and [2] high, then CLR=[1] or [2], or CLR=/([0] or [3].

(tbc)

Now I wonder if / how easily one can merge states [0] and [1].