I'm currently in the process of learning FPGA development and since information security is a big interest of mine I decided to implement a parallelized DES-cracker on a Altera DE2i-150 FPGA development board.
This board features a x86 system with an Intel Atom N2600 processor and a Cyclone IV EP4CGX150 FPGA with a hard PCI-Express core, hooked up to the x86 system via PCI-Express, which is an excellent opportunity to learn Linux kernel driver development as well. A Linux application will communicate with a controller in the FPGA, fetching status information and controlling the cracking process.
I have de2i-150 fpga development board. Recently, I implemented DES Cracking Project using this board. I designed parallel pipelined des engine. There were 32 des engine on fpga chip. As a result, it takes 4 months to crack 56bit des. I want to join this project. Please contact me.
I'm really happy to see this task.
I have de2i-150 fpga development board. Recently, I implemented DES Cracking Project using this board. I designed parallel pipelined des engine. There were 32 des engine on fpga chip. As a result, it takes 4 months to crack 56bit des.
I want to join this project.
Please contact me.