I have solved the issues that came to light over the last few days with respect to Trinity Net.
So I will go through them.

1. Incorrect reflection wiring within the array interconnect on two levels.

2. Node ID X and Z swapped.

3. Direction Selection encoding swapped the Z component so that it went in the opposite direction to that intended.

4. For simple header only messages there were multiple writes to memory.

The next stage stuff will look at the following.

1. Make the direction selection aware that the nodes are in a loop so it can use an optimal routing rather than the simplistic dumb routing it has now.

2. Write a kind of Monitor that each node can run up and accept some form of instruction code and run it.

3. To put in a method to allow the system discover it's own size. This might be a mixture of software and hardware.

4. Expand the Assembler so that it can accept more instructions and decide if a 'smaller' instruction can be used instead.

5. Implement the 8 bit instruction look up capability.