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A project log for Trinity Core and Net

A 32 Bit Variable Length Instruction Set Core and Transputer Like Comms Network

andre-powellAndre Powell 01/28/2017 at 18:300 Comments

There have been a few developments.

The Perl Assembler has been updated in the following ways.

1. The introduction of the 'vector' key word to place vector information at the start of the data memory. This provides the Exception Vector Table.

2. The introduction of the 'text' key word which provides the ability to create text and put it into the Data memory, the text can be defined as having a carriage return or just a continuation.

3. Enabling Call Imm instruction and enabling the use of labels.

The following software routines have been written.

1. Creating a 'Putchar' routine.

2. Creating a routine that will take selected text and then send it character by character to the Putchar routine.

3. The creation of a hex to ascii routine to all the display of hex values.

On the hardware side

1. Re-enabling Pushf and Popf, initially mothballed for speed examination.

2. Discovery of a bug in the Prefetch that cause the incorrect creation of a PC and a rogue instruction. Now fixed.

3. The Branch Prediction seems to be working well.

Plans for the future.

1. Creating a Nested Interrupt Block.

2. A Non Blocking Memory Infrastructure to allow multiple masters.

3. A DMA Block which should make each node more efficient.

4. Code to run on a Master to dispatch Program code.

5. Code to run on a Slave to accept and run it (note a bit more than the ad hoc code to prove the concept).

So it's not over yet by a long chalk.

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