I now have a first cut nested interrupt controller and will need to test it. There is an initial interrupt conditioning block so that interrupts can be pulse, level and asynchronous. The conditioning set up via registers. It can have up to 256 interrupts at present but in theory it can have a programmable at build number.

Assuming this is all ok I just need to write a simple gpio block and maybe a Hitachi LCD Text driver rather than a bit bash code I got to display "Hello World" wayyyy back.

After that I can put together a

"Processor Complex"

which will have the main features of a minimal micrcontroller by adding in the DMA, Interrupt Controller, Non Blocking Interconnect and the Open Cores UART.

This will allow me to place the elements into a small and thus cheap FPGA board to allow deployment into projects.

The Multicore environment will not be forgotten, I still have plans for this, initially formalising the system so that it is extracted from the testbench enviroment and become a deployable bit of IP with an enhanced Master Core.