Unfortunately, a small issue has been brought to my attention. When the duty cycle is either very low or very high, the frequency measurement may be incorrect. This happens when the duty cycle is less than about 12% or greater than about 88%.

It takes about 128 microseconds to perform an ADC conversion. Since the frequency is 1 kHz, that means one whole cycle is 1000 microseconds. 12.8% of that is... 128 microseconds. That means that any duty cycles where the positive-going or negative-going portion is shorter than that might wind up getting skipped over. That means that two transitions won't be counted, and the frequency will read low.

The fix for this is to configure the analog comparator to be the frequency counter using interrupts. Unfortunately, this can't be done without some changes to the hardware, since the only available internal comparison source is the bandage reference, which equates to an input voltage of something like -10.5, which is way too low. Additionally, for the ATTiny84 (used on the display variant), you can't use the ADC MUX output for the analog comparator while the ADC is enabled.

The only fix is to free up the two analog comparator pins and provide a reference on the negative input that corresponds to something close to zero volts. As it turns out, this is around 2.75 volts or so, which we can make with a 10kΩ/12kΩ voltage divider. AIN0/00 can be configured as both the positive input to the comparator and the input to the ADC. The ISR can just increment the high, low and change values in the ISR as appropriate.

We can still perform ADC operations to determine the high and low peak voltage. The ISR of the AC will insure we never miss a transition, and with something like 7000 samples per second, the changes we will miss both the positive and negative edges is minute for any legal J1772 duty cycle.