If you saw my bit earlier, you'll know that I received my first set of PCBs today. I setup some time after unwinding from work to grab hi res photos of the boards so it'd be easier to QC areas that I know were very tight on tolerances and could be a problem. Some, like the mDP connectors, are unavailable at this time. Others, I just have to be careful and/or use a lab that has tighter tolerances.
Here are adjusted photos that show the areas I have to examine on each board:
Top side:
- Traces between C1 and C2 for the 3.3V rail. I copied the basic layout for this SMPS topology from the manufacturer's data sheet as well as I could.
- C3 was a "Ooops, did I really do that?" as it's covered by the inductor. I shouldn't have any issues and fudge the location of both a little.
- MIddle of the board is a via for ground planes.
- Far right are the set of vias that caused me to use the min drill size, 13 mil, to help try and avoid clearance issues. This is for the SRAM chip so it's kinda a show stopper if there is a problem an Xacto knife cannot fix.
- The closest pairs of through hole pads for the mDP connectors are about 2 mil too close. It just dawned on my that I can manually space them further without issue...
Bottom side of the board problem areas:
- The trace length matching in the upper left have a couple bumps that are very close to their neighbors, but I don't see an issue.
- Vias just to the left are a big concern because I am really tight on space there and used the min drill of 13 instead of the normal 15 for every other small via.
- A particular by pin 1 of the PIC32MX is routed very close to the via and the pin itself buy about 2-3 mils.
- 2 other misc vias
- Diodes are missing polarity silk screens because I put them on top of the traces in the upper right.
- Down and to the left of those, I realized that the accelerometer footprint was well under the tolerances, but they seem to have printed it anyhow. I may or may not add it onto the board on this prototype.
In general, I know that there are no plated slots on the board. They are structurally required for the USB ports and mDP receptacles. At the moment I'm going to live with it and use a dremel to trim the parts a tad.
High res photos of each board, from and back. They are 2000 pixels tall and ~3600-3700 pixels wide. They've been edited for contrast and inspection. If you think you see a problem, feel free to speak up.
Board 1
Board 2:
Board 3
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Osh Park does produce good boards, though going all of the way down to the lab's tolerances runs to risk of bridging and other issues.
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