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• Standalone Version of Eight-Input Channels ScopeIO Controlled by Four Buttons

  Miguel Angel • 08/23/2024 at 03:52 • 0 comments

• USB real-time configuration handshake capture

  Miguel Angel • 08/23/2023 at 22:47 • 0 comments

  USB device communication link for #hdl4fpga is operational

• USB core for SIO

  Miguel Angel • 07/08/2023 at 00:01 • 0 comments

  Some progress has been made on the USB core. The request set_address and get_descriptor are now recognized. The device_descriptor is successfully read by the PC. The Wireshark capture complies with the captured frame 

  data-capture screenshot data is little endian

  Wireshark screenshot

  The captured frames screenshot is a raw bitstream with bit stuffing extraction. CRC is included. Octets are MSB first. The screenshot data capture is done on the ULX3S board using HDL4FPGA's ser_debug app. You can find the LatticeDiamond project file at https://github.com/hdl4fpga/hdl4fpga/blob/dev/boards/ULX3S/diamond/apps.ldf. The active implementation is ser_debug

  USB core is now detected by Linux
  

• Orangecrab was added to the project

  Miguel Angel • 05/26/2023 at 22:51 • 0 comments

   Graphics was ported to the orangecrab  https://github.com/hdl4fpga/hdl4fpga/tree/dev/boards/orangecrab 

• When leds are not enough

  Miguel Angel • 05/11/2023 at 17:09 • 0 comments

  Display testpoint values on screen. It helped me to find deadlock bug on the UDP comm system.

  https://discord.gg/66M5QX4

  Project files  can be found on 

  https://github.com/hdl4fpga/hdl4fpga/tree/2a0e459e2c5e06b068ccb8dec8f681b24327e238

  library/basic/base.vhd
  library/basic/dpram.vhd
  library/video/videopkg.vhd
  library/video/tmds_encoder.vhd
  library/video/cgafonts.vhd
  library/video/cga_rom.vhd
  library/video/cga_adapter.vhd
  library/video/fonts/bcdfonts.vhd
  library/video/fonts/cp850x8x8x0to127.vhd
  library/video/fonts/cp850x8x8x128to255.vhd
  library/video/fonts/cp850x8x16x0to127.vhd
  library/video/fonts/cp850x8x16x128to255.vhd
  library/basic/latency.vhd
  library/basic/rom.vhd
  library/video/video.vhd
  library/video/dvi.vhd
  library/basic/serlzr.vhd
  library/basic/barrel.vhd
  library/sdram/phy_iofifo.vhd
  library/apps/app_profiles.vhd
  library/apps/ecp5_profiles.vhd
  library/apps/ecp5_videopll.vhd
  library/basic/fifo.vhd
  library/basic/sync_transfer.vhd
  library/basic/adder.vhd
  library/basic/txn_buffer.vhd
  library/apps/display_tp.vhd

  Example of usage 

  library ieee;
  use ieee.std_logic_1164.all;
  
  entity ulx3s is
      generic (
          debug : boolean := false);
      port (
          clk_25mhz      : in    std_logic;
  
          ftdi_rxd       : out   std_logic;
          ftdi_txd       : in    std_logic := 'U';
          ftdi_nrts      : inout std_logic := 'U';
          ftdi_ndtr      : inout std_logic := 'U';
          ftdi_txden     : inout std_logic := 'U';
  
  
          btn_pwr_n      : in  std_logic := 'U';
          fire1          : in  std_logic := 'U';
          fire2          : in  std_logic := 'U';
          up             : in  std_logic := 'U';
          down           : in  std_logic := 'U';
          left           : in  std_logic := 'U';
          right          : in  std_logic := 'U';
  
          led            : out std_logic_vector(8-1 downto 0);
          sw             : in    std_logic_vector(4-1 downto 0) := (others => 'U');
  
  
          oled_clk       : out   std_logic;
          oled_mosi      : out   std_logic;
          oled_dc        : out   std_logic;
          oled_resn      : out   std_logic;
          oled_csn       : out   std_logic;
  
          --flash_csn      : out   std_logic;
          --flash_clk      : out   std_logic;
          --flash_mosi     : out   std_logic;
          --flash_miso     : in    std_logic;
          --flash_holdn    : out   std_logic;
          --flash_wpn      : out   std_logic;
  
          sd_clk         : in    std_logic := '-';
          sd_cmd         : out   std_logic; -- sd_cmd=MOSI (out)
          sd_d           : inout std_logic_vector(4-1 downto 0) := (others => 'U'); -- sd_d(0)=MISO (in), sd_d(3)=CSn (out)
          sd_wp          : in    std_logic := '-';
          sd_cdn         : in    std_logic := '-'; -- card detect not connected
  
          adc_csn        : out   std_logic;
          adc_mosi       : out   std_logic;
          adc_miso       : in    std_logic := '-';
          adc_sclk       : out   std_logic;
  
          audio_l        : out   std_logic_vector(4-1 downto 0);
          audio_r        : out   std_logic_vector(4-1 downto 0);
          audio_v        : out   std_logic_vector(4-1 downto 0);
  
          wifi_en        : out   std_logic := '1'; -- '0' disables ESP32
          wifi_rxd       : out   std_logic;
          wifi_txd       : in    std_logic := '-';
          wifi_gpio0     : out   std_logic := '1'; -- '0' requests ESP32 to upload "passthru" bitstream
          wifi_gpio5     : inout std_logic := '-';
          wifi_gpio16    : inout std_logic := '-';
          wifi_gpio17    : inout std_logic := '-';
  
          ant_433mhz     : out   std_logic;
  
          usb_fpga_dp    : inout std_logic := 'U';  
          usb_fpga_dn    : inout std_logic := 'U';
          usb_fpga_bd_dp : inout std_logic := 'U';
          usb_fpga_bd_dn : inout std_logic := 'U';
          usb_fpga_pu_dp : inout std_logic := 'U';
          usb_fpga_pu_dn : inout std_logic := 'U';
                         
          sdram_clk      : inout std_logic;  
          sdram_cke      : out   std_logic;
          sdram_csn      : out   std_logic;
          sdram_wen      : out   std_logic;
          sdram_rasn     : out   std_logic;
          sdram_casn     : out   std_logic;
          sdram_a        : out   std_logic_vector(13-1 downto 0);
          sdram_ba       : out   std_logic_vector(2-1 downto 0);
          sdram_dqm      : inout std_logic_vector(2-1 downto 0) := (others => 'U');
          sdram_d        : inout std_logic_vector(16-1 downto 0) := (others => 'U');
  
          gpdi_d         : out   std_logic_vector(4-1 downto 0);
          gpdi_dn        : out   std_logic_vector(4-1 downto 0);
          gpdi_cec       : inout std_logic := '-';
          gpdi_sda       : inout std_logic := '-';
          gpdi_scl       : inout std_logic := '-';
  
          gp             : inout std_logic_vector(28-1 downto 0) := (others => 'Z');
          gn             : inout std_logic_vector(28-1 downto 0) := (others => 'Z');
          
          gp_i           : in    std_logic_vector(12 downto 9);
  
   user_programn : out std_logic := '1'; -- '0' loads next bitstream...

  Read more »

• new tmds_encoder and dvi module

  Miguel Angel • 04/29/2023 at 03:17 • 0 comments

  tmds_encoder and dvi modules working on any DDR gear. 

• Changing repository layout and editing some documentation

  Miguel Angel • 04/23/2023 at 06:54 • 0 comments

  app_graphics documentation improved. https://github.com/hdl4fpga/hdl4fpga/wiki/App-Graphics
  

• DDR core

  Miguel Angel • 04/23/2023 at 06:52 • 0 comments

  DDR core exceeds or equals that of the manufacturers in Xilinx spartan 3, virtex 5, artix, Latticesemi ecp3, ecp5.

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