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Hack Chat Transcript, Part 3
Lutetium • 08/28/2019 at 20:05 • 0 comments

Ken Gracey (Parallax)12:55 PM
@Chip Gracey - marketing question! What's the ideal application? Do you foresee people using it as general-purpose or for a specific app? Maybe some of the forum members can share ideas.

Frank Buss12:56 PM
I think this interactive programming style would work best in combination with APL :-)

Boian Mitov12:56 PM
Ahem... @Chip Gracey I am looking, but I don't see the P2 as a Hackaday IO project ;-)

monsonite12:56 PM
@Chip Gracey I have been following your work for perhaps 15 years - and I am so pleased that P2 is coming to fruition. I totally buy into your educational ethos, and I hope that P2 will give more power to the next generation of engineers and creatives

Boian Mitov12:56 PM
Maybe you can post it and see people posting ideas about it ;-)

engineering12:57 PM
CNC machines and 3D printers along with drone controllers

Boian Mitov12:57 PM
Social platforms are a great way to generate product ideas IMHO ;-)

James Newton12:57 PM
Well, I just said... as a reader for our encoders which must do ATAN2. Multiple cores and A2D chanels means we could support more joints with one chip. Won't beat an FPGA, but might cost a lot less and be useful for the human input device to remote the Dexter robot arm.

Chip Gracey12:57 PM
Ideal application? Not sure. I mainly see it as an inventor's playground, and trust that it will find applications.

Jeff Martin (Parallax)12:58 PM
Thanks @monsonite

Boian Mitov12:58 PM
How it handles Multimedia ? Audio, DSP, Image Processing ?

Boian Mitov12:58 PM
AI is also a very good application, especially for small robots

Boian Mitov12:59 PM
It probably makes a very good small AI platform

Chip Gracey12:59 PM
@james, it might not beat an FPGA in throughput potential, but it would be fast enough and code changes would take 1/500th the effort. A person might go to their grave getting Verilog code ironed out.

Jac Goudsmit12:59 PM
I have several Propeller projects on Hackaday.io/jac but my current project is reverse engineering a Digital Compact Cassette recorder. I think the P1 and P2 would be a good match if it would be easier to bring up the interfaces (SPI, RS-232).

Yann Guidon / YGDES12:59 PM
Chip : then switch to VHDL ;-)

Jeff Martin (Parallax)12:59 PM
Maybe the question is better phrased as What application can the P2 excel at?

Chip Gracey12:59 PM
Yeah, robots are an ideal app.

Chip Gracey1:00 PM
@Yann, yes with VHDL we could retain all the complexity, but type four times as much code.

James Newton1:00 PM
@Chip Gracey we don't use verilog or any text based language for our FPGA programming. totally visual language. wish I could say more, it's still fucking tied up in business shit, but will be open sourced soon.

We're coming up on an hour, which is usually how long we go before giving the host(s) a chance to bail and get back to work. Parallax folks, you're welcome to stay on and keep fielding questions, or to bug out if you need to. Either way, I think we all want to say a huge thank you for your time today!

Hack Chatters, don't forget next week's Chat is "Clean Water Technologies" with Ryan Beltran: https://hackaday.io/event/166179-clean-water-technologies-hack-chat

Frank Buss1:01 PM
I recently tried SpinalHDL a bit, a better alternative to Chisel, which in turn is much better than VHDL or Verilog, makes it really easy to rpogram things for FPGAs (if you know Scala)

dyee-go-bears1:01 PM
Agree w/ comments re: CNC usage. Multiaxis motor control for p2, along with lots of sensor inputs, seems like a straightforward educational use. But eventually, practically speaking, you end up using a "real" motor controller in a production setting. I'd like to see how P2 compares to something like Jetson when it comes to AI / ML.

Jerry Hubbell1:01 PM
I have developed the PMC-Eight system for Explore Scientific which is an astronomical robotic mount controller...
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Hack Chat Transcript, Part 2
Lutetium • 08/28/2019 at 20:04 • 0 comments

Chip Gracey12:29 PM
@IRC, no, SD boot would take longer. I'm talking about an 8-pin serial Flash.

IRC12:29 PM
[Kamilion] normal old SPI NOR, winbond 4-bit style.

IRC12:29 PM
[Kamilion] Gotcha.

Ken Gracey (Parallax)12:29 PM
Hey @Joshua Donelson so good to see you here. Initial languages most likely: Spin2, MicroPython. BlocklyProp not determined. C a possibility for our development (required to get Python). This sausage is still getting made, on the Forums, within Parallax and by all of you.

IRC12:30 PM
[Kamilion] yeah, right now micropython is running on top of a RISCV ISA simulator (and still rediculously fast)

IRC12:30 PM
[Kamilion] i think someone else was working on a native port as well

Jeff Martin (Parallax)12:30 PM
@Joshua - We are encouraged by all the forum interest in getting other languages implemented. MicroPython, Spin, C. We haven't decided yet when we'll implement Blockly and what language(s) it will generate.

pvoss12:31 PM
Yes, P1 reliably runs at -40C/-40F. I believe I had a P1 payload operating down to -50C once, but will need to check. The lipo batteries really die at these temps, so likely the P1 was not the issue when the payload stopped transmitting.

Chip Gracey12:31 PM
The P2 has deep debugging hooks, so I look forward to making a very fast Spin2 compiler (hit the key and your code is running 100ms later), with a really thorough and interactive debugger. The more you can quickly see and interact with your code, the better stuff you can make.

David Carrier12:31 PM
When start-up time is critical, it would be pretty easy to chain load from flash to an SD card, and do timing-critical initiation from flash, while the SD card code is booting in another cog.

JDat12:31 PM
to solve motor driver problem while booting, use external pullup or pulldown resistors. Yes it is assitional complexy to schematics, but safety first! On any MCU. P2 can work in two stage bootloading. Boot quickly minimal code from EEPROM and set-up safety. Then boot from SD card.

Joshua Donelson12:31 PM
@Ken Gracey (Parallax) Thanks, that is a great way to do it.

JDat12:31 PM
Like in good old P1 times.

IRC12:32 PM
[Kamilion] JDat: the start up delay comment was more about FPGAs requiring time to load the bitstream before being ready to rumble; just so we're crystal

James Newton12:32 PM
@JDat what happens is that users don't understand the need for bootup time and fail to include those pull resistors. Of course they should... but people don't always.

Joshua Donelson12:33 PM
@Jeff Martin (Parallax) Personally I like the text programming methods over the graphics style, so Spin, C, Python are all good with me. :)

Yann Guidon / YGDES12:33 PM
Antifuse or Flash-based FPGA (from ex-Actel) have no startup time problems :)

IRC12:33 PM
[Kamilion] yeah, my personal preference is using the micropython REPL to live-code

JDat12:33 PM
in FPGA/CPLD it can be solved with zero boot time models

Chip Gracey12:34 PM
Text programming is hard to beat, once you know what you're doing. It's amazing how much can be expressed compactly with 7-bit ASCII.

David Carrier12:34 PM
We have BLDC servo motor drive in our to-do list, so it could just be a matter of implementing our reference design and having the FET drivers connected straight to I/O pins.

Ken Gracey (Parallax)12:35 PM
Interested to know if all of you see Python for P2 as primarily intended for an educational audience, or for commercial product development? Of course, you may ask "but what other languages could I choose from?" But I ask primarily about the role of MicroPython and P2, based on what you know, think, prefer.

Kamilion12:35 PM

IRC12:35 PM
[Kamilion] kbIDE's been getting a lot better recently.

hologram7012:36 PM
I have lots of programs written in PropC ... will they run on P2 ?

IRC12:36 PM
[Kamilion] Generally, I'm happy with micropython as long as _thread...
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Hack Chat Transcript, Part 1
Lutetium • 08/28/2019 at 20:03 • 0 comments

Ken Gracey (Parallax)11:56 AM
The Chip-beacon has sounded; he is on his way. . .somewhere.

Welcome everyone, thanks for joining the Hack Chat today. We've got Ken and Chip Gracey from Parallax here today, ready to answer all your questions.

Ken, Chip - welcome aboard and thanks for taking time out of your day for us. Looks like we have Jeff Martin too?

engineering joined the room.12:01 PM

David Carrier12:01 PM
Jeff Martin and I are both here, from Parallax.

Ken Gracey (Parallax)12:01 PM
Chip is still logging in; password update and here he comes. Yep, you have Jeff Martin and David Carrier here as well.

Todd Christell joined the room.12:01 PM

Chip Gracey12:02 PM
Okay, I think I'm in.

Welcome to all the Parallax team then! Thanks for joining us today.

Ken Gracey (Parallax)12:02 PM
Jeff has developed our software tools for 20+ yrs and participated in P1 design; David does firmware, PCB design, manufacturing support and anything else. Fozzie is here.

Jeff Martin (Parallax)12:02 PM
Hi everyone!

Boian Mitov12:02 PM
Hello @Chip Gracey

IRC12:02 PM
[Kamilion] Hi guys! Guess the first question is, how are things looking with the die test at onsemi? We're all awaiting the P2 for xmas with baited breath.

Chip Gracey12:03 PM
Hello, Boian.

knikula joined the room.12:03 PM

engineering12:03 PM
Jim (Publison) here to provide bodygaurd provisions for Ken ana Chip

IRC12:03 PM
[de∫hipu] bated breath

James Newton12:03 PM
Hi Ken, Chip. Wanted to say I'm a huge fan of Chips work. I ran sxlist.com back in the day and appreciated being able to translate PIC code to SX and run it 4x faster. (or nearly 4X, jumps killed the que of course)

Yann Guidon / YGDES12:03 PM
hmmmm it smells like ASIC here :-)

pvoss joined the room.12:04 PM

Ken Gracey (Parallax)12:04 PM
Chip will answer the die-testing question; I'll address the availability of chips by ChipMas.

Chip Gracey12:04 PM
Well, the chips we got back, initially, work great. However, ON Semi started running into lots of trouble testing the remaining wafers. It turns out that we have a latch-up problem in the I/O circuit that will require a slight redesign.

Joshua joined the room.12:04 PM

David Carrier12:04 PM
James, I am glad sxlist is still running, I used it to find something last year, when working on an SX project!

Ken Gracey (Parallax)12:05 PM
ON Semi has about 1K die (possibly more) which are engineering samples we will soon have packaged. They plan on getting the packaging done after they unravel the current testing issues with Chip. At that time, we're looking at about 7 weeks from release to packaging.

Yann Guidon / YGDES12:05 PM
chip testing can look dull but it's actually something I focus on in some of my Hackaday projects, so please elaborate and explain you workflow :-)

James Newton12:05 PM
Huge fan of Kens work as well, but the chip work (see what I did there?) was amazing.

djl joined the room.12:05 PM

Chip Gracey12:05 PM
The chips that we have here work better than anticipated, since the PLL got cleaned up and the new clock-gating cut the power consumption in half.

IRC12:05 PM
[Kamilion] aye, I've been following along on the forum with the die tests; and watched the call go out to P2-ES gloptop owners to check the IO resistances

Yann Guidon / YGDES12:06 PM
clock gating ? swwweeeeeet :-)

IRC12:06 PM
[Kamilion] I'm still in awe y'all managed to blow past 300Mhz for a fMAX of 185Mhz/85C

Ken Gracey (Parallax)12:06 PM
These 1K chips could easily help us build another 250 Propeller 2 Evaluation Boards and accessories. I think it's realistic to say we'll have these boards available ChipMas (if I have to guess) so we all have something productive to do when relatives come over.

IRC12:06 PM
[Kamilion] reminds me of the old Celeron 300A -> 450Mhz

engineering12:06 PM
Chip, were the Rev1 chips...
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