I'm happy to report that I've completed the CSR Unit, or CSRU for short.  This is the block of logic which implements all of the CSRs (Configuration and Status Register) mandated by the RISC-V Privilege Spec 1.10 as of this posting.

It's my first real implementation of logic using nmigen as a hardware development tool.  And, I must say, I'm really quite impressed with it.

The CSRU takes up 1157 of the 7680 logic cells of the iCE40HX8K FPGA.  This might well be entirely too big for the finished design, however.  If I remove all of the performance counters, some of the useless read-only registers like MARCHID and MVENDORID, etc., I can drop the resource consumption down to 769 LCs.  And, I can reduce this still further by ignoring the priv-spec requirement for WLRL fields (treating them instead as WARL fields, as the original KCP53000 does), which will let me throw away 59 of the DFFs used to build out the MCAUSE register, just to name one example.

Also, with the CSRU as-is, the fastest clock speed is just a smidge above 50MHz.  This isn't very much, unfortunately; once the rest of the processor is implemented, I predict the completed processor circuit will need to be clocked somewhere in the 16MHz to 25MHz range.  Of course, reducing the CSRU complexity will help drive maximum clock speeds higher, but not by much (52MHz in the above example reduction); and, it'll come at the cost of no longer being compatible with the RISC-V priv-spec.

For now, I'm going to stay the course with the 1157 LC design, knowing that it's just a few small tweaks to the source code to enable or disable certain features.  Using a higher-level HDL representation like nmigen is a big confidence booster for experimenting with different design configurations later on.

Next Steps

According to my personal project plan, my next step is to work on the Integer Execution Unit, or IXU.  This is the state machine logic that handles actual instruction execution.  It'll accept instructions from an instruction queue (IQ), rather than fetch them directly.  It'll also be responsible for helping to detect and act upon interrupts and synchronous trap conditions as well.