Tonight, I completed the memory stage of the 5-stage pipeline for the Redtail microarchitecture used by Polaris CPU. I then decided, let me run it through Yosys to get a ballpark idea of how many logic cells this thing will use. Pleasantly, I found it needed only 165. Not bad!

Then I figured, "Let's look at the register file."

What I found was that the 32-deep, 64-bit wide, 2-read-1-write register file that you would typically find in just about any RISC consumes 5666 logic cells in an iCE40-class device. This immediately rules out the 4K FPGAs that I was planning on using for the Backbone implementation of the Kestrel-3. By my math, I was banking on it needing around 2500 cells. 5666 is just too much. I'm guessing it needs this many logic cells because the chip doesn't have sufficient routing resources, and Yosys had to resort to using LUTs as wires. Not only that, but for a chip capable of handling 500MHz clocks off its PLLs, the top speed that the register file could work at is only 42MHz (according to the estimate provided by the icetime command). This, alone, means that the Backbone bus clock will need to drop to 25MHz.

Ouch!!

I next figured, let's look at the ALU. This required a gob-smacking 1726 logic cells. Again, I didn't expect it to be ultra-tiny, but this is just too big. That's more than half of the logic cells found in a iCE40HX-4K. And this is just the ALU; this doesn't even consider the magnitude comparators needed in the execute stage for conditional branching support.

Thankfully, instruction fetch takes only 65 logic cells, and decode needs only 212. At least I can be proud of something.

So, the writing is on the wall; if I want a CPU that fits in a 4K device, and I do, then my previous estimates about its performance are right out the window. Gone. Kaput.

I simply must architect it like the 6502, using hardwired state-machines or vertical microcode in place of a 5-stage pipeline. The register file must be single-ported to eliminate as many wires as I can (at the expense of two extra cycles per instruction: one to fetch an operand, and one to write the result back). The ALU and magnitude comparators have to be written at the gate and/or LUT4 level; I cannot trust the Verilog compiler or Yosys to produce the most efficient logic possible. Finally, the entire microarchitecture has to be tailored just for the 16-bit Backbone bus it'll connect to. This may mean I have to shrink the ALU to just 16 bits. Yuck.

I was really, really, really hoping I didn't have to go this route. With a CPU that delivers around 1.5 to 3 MIPS performance (thanks to the lack of a pipeline), the computer will feel about one quarter to one half as fast as a Commodore 64, which I think is unacceptable for a general purpose hacking computer. But, I don't know what else I can do. :( :( :( :( :(