I'm currently trying to re-implement the Polaris CPU once more (as I said I would in a previous log), using a combination of hand-written Verilog and generated code from SMG, codeveloped in a step-by-step fashion. You might not be able to get much information from the diagnostic trace below, but you might be able to discern that IADR is the instruction address bus (specifically, the lowest 32-bits of it). Notice that the core fetches an instruction from $FF...FFFF00, and four cycles later, attempts another fetch at $FF..FFFF04. Polaris just executed its first ever RISC-V instruction!! (BTW, it was a NOP: ADDI X0, X0, 0 in case you were wondering).

@S SCENARIO 1 (16'h0001)
@D -TIME- CLK ... ISIZ IADR     JAM
@D    310  1  ...  00  00000000  1
@D    320  0  ...  00  00000000  1
@D    340  1  ...  00  00000000  0
@D    360  0  ...  00  00000000  0
@D    380  1  ...  10  ffffff00  0
@D    400  0  ...  10  ffffff00  0
@D    420  1  ...  00  00000000  0
@D    440  0  ...  00  00000000  0
@D    460  1  ...  00  00000000  0
@D    480  0  ...  00  00000000  0
@D    500  1  ...  00  00000000  0
@D    520  0  ...  00  00000000  0
@D    540  1  ...  10  ffffff04  0 

I'm excited almost to tears, as followers of this project will probably guess if they paid attention to my logs to date. Polaris implementation has given me nothing but heart-ache for almost a full year. To finally have come across a development approach that actually works (made possible thanks to the SMG state machine to Verilog generator tool I also wrote) makes me so very happy, you have no idea.

Back to hacking; I need to implement other ALU operations besides ADDI before I declare this night a complete victory.