While on the flight yesterday, I wrote the Verilog implementing the Wishbone bus master interface for fetching a scanline's worth of data (the "video fetcher"). As of this writing, the cgia branch is not merged to master.

I'm thinking of moving it into its own repository though, especially since it can be useful for any Wishbone compatible system, and not just the Kestrel-3. I'll post a link here when that happens.