Samuel A. Falvo IIAfter several attempts at writing my own RISC-V CPU implementation in Verilog, I'm officially giving up. I've utterly had it.
Instead of showing up to the RISC-V workshop completely empty-handed, though, I've decided instead to implement a 64-bit MISC-architecture (e.g., Forth-language) CPU; this is something I've succeeded in building in the past (albeit only 16-bits wide). On top of this core will sit a 64-bit RISC-V emulator.
The performance hit will be absolutely immense. I estimate, instead of 6 MIPS, I'll get at best 1 MIPS. The computer will, in all likeliness, be unusable for practical hacking purposes at least until I can implement a proper standards-compliant, 64-bit RISC-V core for it.
To have to admit defeat like this makes me feel physically ill. I know that, only 10 years ago, I probably would have/could have succeeded. Today, it seems my mental faculties just cannot handle the complexity behind even what should be a simple, trivial even, RISC CPU.
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On the other hand, the Kestrel-2 used a MISC core as well, so some will see this as a return to my roots. In that sense, I suppose they're right. Still, I hate that I have to pivot so much, and so frequently.
Maybe an insight will come to me and I can optimize the MISC core for RISC-V emulation, and regain some of the lost performance.
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