NOP, LIT8, LIT16, LIT32, SBM, SHM, SWM, and SDM are implemented.

NOP is the no-operation opcode, of course.

LITx loads an x-bit literal onto the data stack.

SxM stores a byte, half-word, word, for double-word value to memory.

In a mere five hours of hacking, I successfully got further with the MISC core than with several months of attempted hacking on the RISC-V core. Note that my relative time commitment for both projects is the same.

Once the MISC core is complete, I have one of two options:

• I can write a software RISC-V emulator on top of the MISC core (as I was threatening to do last log entry), or,
• I can implement a RISC-V instruction predecode stage, as I was threatening to do back in this log entry.

Which route I take remains unclear at the moment, but either way, we will see RISC-V compatibility. A lot of factors will enter into the decision: how easily a predecoder can be written, how much effort it takes to write a new MISC assemble, etc.

Right now, the MISC core is architecturally quite similar to the S16X4 family of processors used in the Kestrel-2: three data stack registers, no return stack. However, this will eventually change to 8-deep data and return stacks, with their corresponding stack permutation instructions, thus making it a true Forth-capable CPU. I'll implement those features only when I have a demonstrated need, though. Right now, my focus is making it even minimally Turing complete.