Using the assembler I wrote in Python, I generated some hex code to store in the synthesized ROM on the FPGA. I also added a clock divider to slow the system clock from 50MHz down to 25Hz. This results in about a half second period between increments of the output vector.

Assembler Code:

lw r4, 176(r0) //value to count to should be stored at this address
lw r3, 177(r0) //increment value should be stored at this address
sub r2, r4, r1
bez r2, 8
sw r1, 252(r0)
bez r0, -8
add r1, r1, r3
sll r0, r0, r0
bez r0, -2

Hex Code:

0 => x"84b0",
1 => x"83b1",
2 => x"2142",
3 => x"5008",
4 => x"c1fc",
5 => x"40f8",
6 => x"0b21",
7 => x"0000",
8 => x"40fe"