It works as it should but I don't know why.
Here is the source code for Falstad :
$ 3 0.000001 0.34903429574618416 58 3 43 R 696 16 696 -16 0 0 40 4 0 0 0.5 w 808 352 808 384 1 w 808 192 808 176 0 w 584 176 584 192 0 w 664 96 592 96 3 w 808 288 808 256 0 w 728 176 808 176 0 w 384 64 384 136 3 w 696 112 696 176 1 w 584 176 664 176 2 w 584 288 584 320 0 w 584 256 584 288 0 w 664 288 584 288 3 w 808 320 808 288 0 w 728 288 808 288 3 w 672 336 728 288 0 w 720 336 664 288 1 r 808 256 808 192 0 1000 r 584 256 584 192 0 1000 t 616 336 584 336 0 1 0.5772267829335654 0.639069922813361 50 t 776 336 808 336 0 1 -1.1769217530853389 0.06184313995994596 50 g 808 384 808 416 0 g 584 376 584 416 0 w 696 16 696 32 1 w 696 32 696 80 0 t 664 96 696 96 0 1 -0.05293572317914741 0.6386489173065311 200 r 384 64 464 64 0 100000 w 496 80 496 96 0 t 464 64 496 64 0 -1 -0.5078879880313893 -0.5343748422129604 100 w 496 32 496 48 0 w 696 32 1160 32 0 r 496 96 592 96 0 1000 w 376 448 376 304 0 d 376 304 440 304 2 1N4148 d 376 256 456 288 2 1N4148 w 496 304 552 304 1 w 552 304 648 304 0 w 696 176 728 176 0 w 696 176 664 176 0 r 776 336 720 336 0 1000 r 672 336 616 336 0 1000 w 648 304 672 336 0 r 512 288 456 288 0 200 r 496 304 440 304 0 200 w 512 288 584 288 1 w 976 288 1048 288 1 r 960 304 904 304 0 200 r 976 288 920 288 0 200 w 1112 304 1136 336 0 r 1136 336 1080 336 0 1000 r 1240 336 1184 336 0 1000 w 1160 176 1128 176 0 w 1160 176 1192 176 0 w 1016 304 1112 304 0 w 960 304 1016 304 1 d 840 256 920 288 2 1N4148 d 840 304 904 304 2 1N4148 g 1048 384 1048 416 0 g 1272 384 1272 416 0 t 1240 336 1272 336 0 1 -0.5571041332660905 0.05744512506309504 50 t 1080 336 1048 336 0 1 0.5113871189769901 0.5688322439565177 50 r 1048 256 1048 192 0 1000 r 1272 256 1272 192 0 1000 w 1184 336 1128 288 0 w 1136 336 1192 288 0 w 1192 288 1272 288 3 w 1272 320 1272 288 0 w 1128 288 1048 288 3 w 1048 256 1048 288 0 w 1048 288 1048 320 0 w 1048 176 1128 176 2 w 1192 176 1272 176 0 w 1272 288 1272 256 0 w 1048 176 1048 192 0 w 1272 192 1272 176 0 w 1048 352 1048 384 1 w 1272 352 1272 384 1 w 1160 32 1160 80 0 t 1128 96 1160 96 0 1 -3.9999999998995 -0.3359971915536067 200 w 1128 96 1064 96 3 r 968 96 1064 96 0 1000 w 1160 112 1160 176 1 w 376 448 1112 448 0 w 384 136 968 136 0 w 968 136 968 96 0 w 664 288 704 256 0 w 840 256 704 256 0 w 808 288 840 304 0 w 1112 448 1184 336 0 w 1136 336 1160 472 0 w 1160 472 352 472 0 w 352 472 352 256 0 w 352 256 376 256 0 w 496 32 696 32 0 R 384 136 336 136 0 2 10000 2 2 0 0.5 w 584 352 584 376 1 o 94 2 0 4355 5 0.00009765625 0 2 94 3 o 14 2 0 4355 1.25 0.0015625 0 2 14 3 o 85 2 0 4355 1.25 0.0015625 0 2 85 3 o 53 2 0 4355 1.25 0.0015625 0 2 53 3 o 67 2 0 4355 1.25 0.003125 0 2 67 3
But when I change anything, it breaks... Worse, it can also create weird chaotic oscillations in some uncontrolled cases.
Metastability (when both transistors in a pair are ON) is a big problem as well... So I played with a capacitor to create some tiny imbalance but it was not the most efficient method.
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I think you have very little noise margin due to direct connection of a collector to the other base. IIRC Vbe of a Ge transistor is -0.3V and I have difficulty finding the Vce(sat) but it may also be as high as -0.3V so there is little margin to keep the other transistor off. It may even vary across transistors. You may even need to select transistors. So a simulation may or may not reflect actual operation.
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yes it's going to drive me insane if I ever try to implement it on the bench...
That's why I have selected a different method, with a different inspiration and using a complementary pair to build a pseudo-SCR :-)
There are other approaches as well but I doubt I can do less than 3 transistors per latch (thus 6 per D-FF), thanks to using a "pass transistor" that works in both directions :-D
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Looking forward to your UART. Now that would be something!
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