It's nearly springtime, when a middle-aged man's fancy lightly turns towards thoughts of computers constructed from diodes... Seeing some recent posts (I'll have to look around for the links) made me finally realize that 2-stage diode logic gates with AND followed by OR is functionally identical to the AND/OR matrix found inside PALs, GALs, PROMs, and all the other simple programmable logic out there. See the diagrams on this page for details. In fact, the sum-of-products computed by this AND/OR cascade can compute any function of the input variables. I don't know why it took me so long to realize it. Using this formulation, a ROM with diode-decoded address lines looks like this:

It's a 16-bit ROM of four words of four bits each. An inverted version of each address line is required as an input. I only connected one diode for each word, but you can get the idea. The inputs are required to sink current, which means reversing the output diodes on DDL gates, but that's very easy to do. You need to choose (or eliminate) the pull-up/pull-down resistors depending on the logic circuits you use to drive/read this array.

The main problem with this kind of implementation is fan-out. Each address line may be required to pull down a resistor for each word, which could add up quickly. In a practical implementation, address line buffers might be required for every N words - maybe a PCB with the buffers and some power-of-2 words could be made - like a 32-word ROM board.

Anyway, I finally "got it" with the AND/OR cascade of diode gates. It took long enough :-)

Now, we need a RAM with a similar design...