Now that electrical connection works, it is time to get data signal.

Lvds has 4 differencial signals on 8 pins :
- Chan1+/Chan1-
- Chan2+/Chan2-
- Chan3+/Chan3-
- Clock+/Clock-

The protocol is not so complicated : just send one pixel after another, and some sync signal (Vsync and Hsync). Since the panel has a fixed size (1024x600), the clock must match the desired screen refresh rate :
Clock = ((width+hsync) x (height+vsync))/refresh

For my panel :
(1024+280)*(600+25)*60 = 48.9Mhz

I initially used Spartan 3e based board (Papillio One).Xillinx Spartan supports LVDS signaling but there is a constraint in assigning pairs which must be next to each other, the UCF file looks like :

NET "channel1_p" LOC = P40; # A5
NET "channel1_n" LOC = P41; # B10
NET "channel2_p" LOC = P60; # A8
NET "channel2_n" LOC = P61; # B7
NET "channel3_p" LOC = P62; # A9
NET "channel3_n" LOC = P63; # B6
NET "clock_p" LOC = P70; # A12
NET "clock_n" LOC = P71; # B3

Thanks to github, I quickly found an already done Verilog implementation with a parallax sample.
I just needed to adapt to the panel :

parameter ScreenX = 1024;
parameter ScreenY = 600;
parameter BlankingVertical = 25;
parameter BlankingHorizontal = 280;

Finally when everything wired, the panel came back to life !