Update

I rebuilt the paged memory board and the Flash Programmer for a ZIF socket. It allows quick and easy Firmware updates.

Other than a initial glitches for the Flash Programmer (probably still wet from the solder flux solvent), it all works.

Now Where Was I?!

After a long break I have to work out where I was:

Current firmware:

• TTA8_FlashProgrammerSDPv4a

The Interpreter primitives coded:

• inline 
• call
• jmp
• jz
• mov ax,[bx]
• mov [bx],ax
• push ax
• pop ax
• push bx
• pop bx
• xchg ax,bx
• xchg ax,cx
• xchg ax,dx
• xchg ax,sp

and:

• jnz_timer
• jz_sflag

Load program has been coded:

• 80 84
• 81 FD
• 82 85
• 83 FF
• 84 06 (ROM #)
• 85 00

Current programs include:

1. Program 06 is an 8 Bit Counter
2. Program 07 is a 16 Bit Counter
3. Program 08 is Serial Echo

Basically I remember I had to revert to this version of the firmware because I messed up the serial interrupt code. So I was working on the Interrupt and Serial code.

Minor Firmware Updates

Looking at how to read/write between RAM pages. I had made provision in the CPU model but had still to update the Interpreter. Done! Now the Interpreter updates the RAM_Page and ROM_Page registers when the ROM or RAM changes. Looking through my notes I see that I have written a standard for long pointer read/writes (i.e. between pages). Currently the Interpreter can only read/write inside a page. I need to move some code around to make room for long read/writes.

I have this idea to move the Stack to a dedicated RAM page and to add a dedicated Return Stack (with its own RAM page).

Checked the Serial I/O, it works fine.

Updating the firmware is a very slow and repetitive process. I dare not do too much else I may not be able to debug the problem (been there!).

So the next step is to migrate to long pointer read/write.

Okay short and long read/writes done. Next is to move the Stack Pointer to its own RAM page.

Undated the firmware for the new PUSH/POP/CALL/RTN code. Worked first off! Updated the EMU to confirm.

New CPU Model

Considering a closer approximation to the Intel 8080:

• [IP] -> [PP][IP] (i.e. the Interpreter paged memory address)
• [SP]->[RP][DP] (i.e. a return stack and a data stack)
• [HX][LX]
• [EX][DX]
• [CX][BX]
• [AX][FX] (i.e. A and Flags)
• [TX]  (i.e. Temporary registers)

With this in mind I have written MOV A,[C:B] and MOV [C:B],A type instructions where C is the Page and B is  the (RAM) Address.

New CPU model updated. Test with default programs.

Where am I going with this? I am thinking a tiny Forth. The Interpreter is basically an inner loop. So I need a number of primitives, a dictionary and the REPL.

AlanX