PavelThe computer has 32-bit address bus, which provides address space of 4 Gigabytes of memory. This is quite big, taking into account that processor will run at frequencies in range of megahertz. It will take more than half an hour for PC to traverse from address zero to the top of this address space doing only NOPs (they take 2 clock cycles) when running at 4MHz. This is impractical in my opinion. Also, as I intend to use SRAM chips, it will be very big and very, very expensive build, which may not even be capable of work at such speeds reliably.
So there will only be maximum of 16 Megabytes of SRAM (main RAM) installed -- for this only lowest 24 bits of address are needed.
The main RAM address range will be from 0x0000.0000 up to 0x00FF.FFFF. This is just 1/256 of all the address space.
Maybe some time in the future I'll implement some sort of memory management with paging and ability to swap memory to permanent storage, and thus full address range could be utilized.
These 16 MB are the lower memory.
There will also be a chunk of address space where ROMs and I/O is mapped. For future proofing I decided to place it at the very top, in range from 0xFF00.0000 to 0xFFFF.FFFF.
The first megabyte (0xFF00.0000--0xFF0F.FFFF) is reserved for ROMs, where system monitor and standard interrupt service routines are to be located.
The last megabyte (0xFFF0.0000--0xFFFF.FFFF) is for Video RAM -- there 2 video buffers are to be located, they will be switching as described on this section of wiki article (page flipping). The two pages of VRAM will not necessary occupy a whole megabyte, I think that pages 128 kBytes each will be enough. These buffer pages will be on the very top of address space.
The next to last megabyte (0xFFE0.0000--0xFFEF.FFFF) is to be reserved for various I/O ports, video control registers, palette and character table.
All the addresses in between will be left unused, there are just so many of them.
Graphical overview of the whole address space:
+-------------------------------------+ FFFF FFFF | ROMs, I/O, video RAM | 16MB higher memory +-------------------------------------+ FF00 0000 | | FEFF FFFF ~ No hardware mapped here ~ ~ May be used for virtual addresses ~ | | 0100 0000 +-------------------------------------+ 00FF FFFF | Main RAM | 16MB lower memory +-------------------------------------+ 0000 0000
Graphical overview of the higher memory:
+-------------------------------------+ FFFF FFFF | Video RAM | 2 pages 128 kBytes each for display data +-------------------------------------+ FFE0 0000 | I/O | keyboard, PATA, UARTs etc. mapped here +-------------------------------------+ FFD0 0000 | | unused +-------------------------------------+ FFC0 0000 | | unused +-------------------------------------+ FFB0 0000 | | unused +-------------------------------------+ FFA0 0000 | | unused +-------------------------------------+ FF90 0000 | | unused +-------------------------------------+ FF80 0000 | | unused +-------------------------------------+ FF70 0000 | | unused +-------------------------------------+ FF60 0000 | | unused +-------------------------------------+ FF50 0000 | | unused +-------------------------------------+ FF40 0000 | | unused +-------------------------------------+ FF30 0000 | | unused +-------------------------------------+ FF20 0000 | | unused +-------------------------------------+ FF10 0000 | ROMs | EEPROMs with system software (monitor, ISRs) +-------------------------------------+ FF00 0000 | | FEFF FFFF ~ virtual addresses ~
The ROMs and VRAM will not occupy whole Megabyte slots, but placed individually for ease of addressing.
Graphical overview of the VRAM slot:
+-------------------------------------+ FFFF FFFF | page 1 | | (128 kBytes) | +-------------------------------------+ FFFD 0000 | page 0 | | (128 kBytes) | +-------------------------------------+ FFFC 0000 | | | | unused +-------------------------------------+ FFFA 0000 | | | | unused +-------------------------------------+ FFF8 0000 | | | | unused +-------------------------------------+ FFF6 0000 | | | | unused +-------------------------------------+ FFF4 0000 | | | | unused +-------------------------------------+ FFF2 0000 | | | | unused +-------------------------------------+ FFF0 0000 | | FFFE FFFF ~ I/O ~
The video buffer pages are on the topmost ranges.
At any time one of them is used by GPU, or VGA adapter (yet to be designed and built), and the other can be written to by CPU. When the write is done, and right before new frame is started to be drawn on screen, the pages flipped (with the use of small interrupt service routine), and new frame can be composed on fresh page.
This way, the CPU is decoupled from the harsh VGA timings, and can do its things at its own pace.
Graphical overview of the I/O slot:
~ VRAM ~ | | FFF0 0000 +-------------------------------------+ FFEF FFFF | | | VGA controls | +-------------------------------------+ FFED 0000 | | | UART 3 | +-------------------------------------+ FFEC 0000 | | | UART 2 | +-------------------------------------+ FFEA 0000 | | | UART 1 | +-------------------------------------+ FFE8 0000 | | | UART 0 | +-------------------------------------+ FFE6 0000 | | | PATA interface | to be used with CompactFlash storage +-------------------------------------+ FFE4 0000 | | | keyboard input | +-------------------------------------+ FFE2 0000 | | | terminal output | +-------------------------------------+ FFE0 0000 | | FFDF FFFF ~ unused ~
The devices may change.
For each device/port there reserved quite a lot of address space, but in reality the whole range will be treated as single address, the lower bits will be discarded. This is done to make addressing circuitry easier, and I have a lot of address space to spare.
Discussions
Become a Hackaday.io Member
Create an account to leave a comment. Already have an account? Log In.