CP/M 50 Mk II

Revision A boards should be back in a week or so.  The first revision required a blue wire to correct an issue with reset and the addition of a resistor and capacitor.  The new revision fixes these issues and also simplifies repurposing the Z8 programming serial port.  New features include RTS/CTS connections for hardware flow control and connecting a previously unused Z8 pin to the L92 RTC clock.  The Z8 clock source is a trimmable internal  precision oscillator and the unused pin happened to be a timer output, so we'll see if the RTC proves to be useful.

The new EDA files will be posted to the projects github repo; with the return of the square inch contest completed, congratulations to the winners, the current EDA files will be removed from the files section. 

If you are contemplating building one of these boards I would wait for the new revision to be released; the rework is a bit fiddly.

Here are a couple of diagrams of the boot process.

1. at reset, push first bootloader into external RAM then reset eZ80 to start first bootloader
2. first bootloader loads second bootloader/disk manager/disk operations binary from microSD
3. second bootloader mounts virtual disks for drives A and B, loads CP/M from reserved tracks of drive A, jump to BIOS coldboot entry point
4. CP/M running, virtual disk access provided by BIOS and mixed-memory mode disk I/O function

The limited amount of flash in the Z8 drives the need for two bootloaders. The largest Flash for an 8-pin Z8 is 8KiB.  The desire to keep the µP and µC Zilog drives the Z8 and the board size drives 8-pins.

The L92's I²C interface along with power and ground are available for external use.

Here are a couple of action shots showing off the Hackaday logo on an I²C 128x64 OLED display.

Here's the I²C pinout.

Just added software repos to the projects links section.