The z80 design is based on Z80SBC64, the '64' refers to Altera EPM7064, but as many Z80 SBC that must had been built over the years, this can easily be the 64th Z80 SBC.  The current trend in low chip-count Z80 SBC is using another processor to provide bootstrap function as well as I/O functions for the Z80.  Such dual-processor architecture requires complex software interaction between the two processors, and the combined throughput of the two processors are less than the throughput of any one of the processors, so it feels like stepping backward in performance and the hardware/software seems harder to comprehend and to modify.  I prefer the traditional computer architecture where Z80 controls everything around it but does it faster and with fewer chips.  The key is using programmable logic instead of TTL logic, but instead of the expensive FPGA that requires 5V-to-3.3V translation, using the low-cost 5V complex programmable logic device (CPLD).  Furthermore, the CPLD has sufficient logic to implement an unusual feature, serial bootstrap, that uses serial port to load the traditional ROM code in RAM resulting in a ROM-less computer.  The ROM-less design eliminates the hassle of ROM programming and further reduces the chip count resulting in a small 2" x 4" pc board.

The original design was prototyped with Altera EPM7128S CPLD, a 100-pin surface mount device that is difficult for most hobbyists to assemble.   Further design refinements allow the final design to fit in a EPM7064S as 44-pin PLCC package.  By hosting the PLCC device in a through-hole PLCC socket, the pc board can be assembled by most hobbyists.  The final Z80SBC64 design is proven with successful construction and operation of 10 or more boards.

The four-stage approach is originally conceived to simplify the assembling and testing process where the partially assembled board can be functionally tested in each stage.  This approach is particularly suited for hobbyists putting together a new board.  It is reassuring to take baby steps and verify things are working in each step.  Another issue is parts ordered may not be available or delivered, but we like to play with the partially assembled system without all the parts.  Furthermore, I believe the learning process is enhanced as limitations and capabilities of the computer at each stage are explored and we learn how new features added in next stage enhances the existing capabilities.

Each of the 4 stages are breakdown into hardware phase and software phase.  The hardware is the assembly phase, and the software is the testing and exploration phase.  The computer is functioning at each stage and gains sophistication as the assembly progresses.  It is not necessary to finish all 4 stages of assembly.  The computer is functioning and may be perfectly suited for certain applications without reaching the end of stage 4. 

Here are brief descriptions of the four stages:

• Stage 1, minimal operating Z80, runs native monitor, SCMonitor, BASIC programs, games
• Stage 2, software are preserved between power cycles, banked memory hardware protects system software from application software.
• Stage 3, compact flash interface and CP/M
• Stage 4, RC2014 expansion bus, interface to RC2014 compatible boards

While the board is capable of 22 MHz operation, it is not necessary to run at 22Mhz.  If only slower Z80, RAM and oscillator are available, it is perfectly fine to run the board at the lower clock frequency.  The serial port baud rate is directly determined by the CPU clock, the table below show the relationship between clock frequency, serial baud, and RAM speed: