I hadn't looked at this project in a long time, and the other day I was browsing it and noticed several comments asking for the schematics. But hadn't I uploaded schematics?  So I double checked the files, found the attached schematic zip, and decided to open it up.  Oh geez, what a mess!  It had been created with a very old KiCad version compared to today, and I don't think I uploaded the symbol libraries, so the schematics were useless.  I can see now why people asked for the schematics!

I spent some time the other day cleaning this up, as well as fixing a few hardware bugs related to the color DAC and oscillator.  I modified the schematic to match the modifications on my board at home, which works quite well.  Here's the schematic now, which I uploaded:

The wires are very messy, consistent with how I made many schematics in highschool.  Clearly, this schematic needs to be redone from scratch.  Well, if I'm going to redo the schematic and roll a new board, why not make a bunch of improvements too?  Well, this is exactly what I've been working on.

Upgrading the board
If you saw my log in #Arduino Desktop, then you'll know that I mentioned this project, in that I may want to add it to another Teensy or ESP32 based computer system.  A Teensy 4.1 could write a lot of data to VRAM very quickly, which would be great for drawing bitmaps, and in-between the uPD7220 can draw other shapes.  In that log I also mentioned double-buffering the uPD7220, so there would effectively be two RAM banks, which could be switched by some command.  To my knowledge, the uPD7220 does not support this, so I needed to add the logic myself.  I'm still working on the schematic, but here's where we are so far:I'm not a huge fan of the old board's low resolution.  I want at least 640x480, if not higher.  Adding more memory for this is quite easy, and in the new schematic this is already handled - the hard part is getting the clock speeds high enough.  The uPD7220 can clock at 6Mhz, and the current card gets this by dividing it out of a 12Mhz clock.  With a Z7220 the clock is a bit higher, 8Mhz and 16Mhz respectively, but this is nowhere near the pixel bandwidth needed for higher resolutions.  My solution to this will be to divide the uPD7220's clock one or two times so we can get 24Mhz or 48Mhz pixel clocks on a uPD7220.  That should allow us to get way better resolutions:
The 800x600 resolution in the above image is a good spot, and uses about half of the VRAM, leaving the other half to be used for double buffering.  I haven't made this part of the circuit yet, and one big thing I'd need to figure out is how to get the right signals to the VRAM for loading the pixels.  I could generate the VRAM's A0 with some logic to load two words out of VRAM each time the uPD thinks it's loading one, but this introduces an issue where the uPD would not be able to draw graphics to half of the pixels.  Perhaps there is a way to have the uPD skip a word each pixel load, then simply modify the A0 line to load this way?  I don't know yet, I need to consult the datasheet and see how this type of thing was done in the past.  I have a feeling they may have used two uPD7220s for this type of thing, but let's see if we can do it without that.  The chips are rare, after all, and the Z7220s are even more rare.

Here is the current clock generator circuit for the new board, which should behave exactly the same as the old board; its job is to generate clocks for the board and to control when pixels are loaded into the output buffer:
Anyway, I have more stuff to figure out with the board.  If any of you have good ideas on the clocks and loading twice the pixels from RAM, let me know :)
Hopefully my schematics are prettier and more useful this time; I think they will be.