• First successful animation....

    Stanislav • 05/06/2019 at 16:21 • 0 comments

    Finally, finished first part of the game and animation and controls(left-right).

  • Finally, my first picture on screen!

    Stanislav • 04/30/2019 at 04:41 • 0 comments

    After the last log update I found a few bugs in my forwarding unit, sometime it was duplicate or delete opcode in pipe. For the temporary fix I cancelled forwarding and left only stalling pipe function. After this compiled all project and flashed it to my fpga and saw nothing on the screen. I spent about 4 days on finding what is wrong with my circuit. I decided to take out some signals from core unit and make a test bench for it and after the short time I discovered that logisim not set properly some register Active level bits in converting to VHDL code. After the fix I finally saw the first picture on the screen and it means that my planning is working!!! 😁

  • Data hazards

    Stanislav • 04/16/2019 at 10:37 • 0 comments

    In pipeline architecture sometimes happens situation when one of the operand don't yet updated, but you need to use it already. For this situations may be 3 solutions.

    1. Stall the pipeline until we get the new value.

    2. Forwarding new value to stage that we need.

    3. (Sofware) Enter NOP commands between the operations.

    I went for 1 and 2. The main idea is to sign every command with 3 additional bits in control unit that will notice the pipe what register is source and another is destination, if opcode is using it.

    We have 8 registers, so we can use another register of 6 bits(3 for destination and 3 for source) to mark and every latch of the stage we sending to data hazards control which doing comparisons of all stages and check if there is source/destination dependnces. If we have dependence between WB and one of the other stages, then we just forward the value, but if we still didn't get the new value from the ALU l, then we will stall the pipe until we got it.

  • Pipeline segments description

    Stanislav • 04/16/2019 at 05:33 • 0 comments

    First update, I already finished hardware implementation of CPU in Logisim simulator. 

    We have there:

    IF segment for instructions. ROM with 16 bit address width. We will not need all of the memory, also Cyclone II don't have such a big amount of memory for implement 64kB. Logisim will create a kind of look-up table in VHDL, for every address value we will get it's data value. I started to write game code in pseudo Assembly and at the moment I have about 150 lines, every command takes 4 bytes. I guess all game will not exceed over 4kb.

    ID segment for register fetching. Here we will navigate all registers to their destination. We have 8 registers: AX, BX, CX, DX, PSW, XP, YP, SP.

    First four is for logic and arithmetic operations. PSW is flags register(zero, carry, sign, parity).

    XP, YP - registers for coordinates on the screen.

    SP - Stack Pointer.

    BC segment is to simplify branch control of the pipeline. The segment calculates branch condition and also new address value to jump in one clock. If branch is take a place then pervious stage is wiped. Near to this segment we have Branch control box for buffer control signal and new address.

    MEM segment - Read/Write memory, 1 byte each time. Also Push and pop commands, we have MUX for switch between memory address and stack pointer registers. Also we will use Dual-port RAM, that means CPU and PPU can access the RAM together and we will not need to control timings.

    EXE segment for logic and arithmetic operations.

    WB for navigation data flow.