After the last log update I found a few bugs in my forwarding unit, sometime it was duplicate or delete opcode in pipe. For the temporary fix I cancelled forwarding and left only stalling pipe function. After this compiled all project and flashed it to my fpga and saw nothing on the screen. I spent about 4 days on finding what is wrong with my circuit. I decided to take out some signals from core unit and make a test bench for it and after the short time I discovered that logisim not set properly some register Active level bits in converting to VHDL code. After the fix I finally saw the first picture on the screen and it means that my planning is working!!! 😁