74HCT6526

Finally, B1 and B2 are completed and they.... kinda work... Although I'm going to have to check quite a few things.

Remember how B0 performed flawlessly, both when connected via the expansion port, and when replacing CIA#2? Well, that's no longer true. I'm getting weird image artifacts when doing that, even using only B0. All registers work OK when connected into the expansion port, so it seems something's wrong with the port outputs. Until I figure it out, I'll do only testing via the expansion port.

Now, about the new boards, I've only been able to do some limited testing. Timers start and stop, and the do count as expected. B0+B1 work, B0+B2 work too. However, if I connect the whole stack (B0+B1+B2) my C64 starts to behave weirdly. I get no cursor and no keyboard. This implies CIA#1 no longer works. I get the startup screen, and Run/Stop+Restore does what it should, so CPU, VIC.. they are pretty much OK. I may be drawing too much power and CIA#1 is the first victim, or some other signal may be being affected.

Something I didn't take into account is how many inputs can I drive from the C64 outputs, and I'm maybe paying for that now.

So, plan for the next couple of weeks. Run some extensive testing on both timers individually, identify why B0 seems won't work properly on its own, and find what's going on when I connect the full stack.

After an uninterrupted successfull streak of 14 months, with no issues at all, this feels weird but... I couldn't be so easy. At least, no C64's had been damaged so far :)

Cheers!

It's been a busy weekend! But here they are. TIMERA on the left, TIMERB on the right. Each one accompanied by its CREG!

The four empty spots on the left of each board are for 4 bit counters, to complete the 16 bit counter for each timer. They should be here this next week.

I've cleared my agenda (it wasn't too busy anyway) this weekend to assemble both B1 and B2, which correspond to both TIMERS and CREG. I'm still missing some ICs (mainly, some 4-bit binary counters) that should arrive soon, so I won't be able to carry out too many tests.

Meanwhile, analisys and design of the remaining units (TOD, SDR and ICR) is around 75% complete. I'm hoping to start working on their schematics by the end of October.

Board 0,  which includes DDRA, DDRB, PORTA, PORTB, and the 65xx bus interface is completed.