I've claimed that this computer is possible to build, it is not only a SW dream. Well, to see if my claims still hold true I've had a go at making a schematic for the memory and bank-switching logic. Using available 74HC-logic and a 512KiB SRAM, I've used 18 chips to make it equivalent to the SW-implementation. While doing this I realise that it id indeed possible to do in HW, but anything faster than 2MHz would probably not work because of all the propagation delays. It would also take up quite some space, even if using surface mounted chips.

If I really want to do this in real HW, an FPGA or CPLD would be a much better choice. Or a ROM of some sort, together with the registers.