I first tried a 16-bit FET carry chain in series just to see what kind of delay we might see. (For reference the test board is configured as follows: R2, R4, R5, R9, R11, R12, R14 and R8 are open and R1, R3, R6, R7, R10, R13 and R15 are closed .. schematic here). Here are the results:

• @ 2.5V, 2.2MHz ==> 14.2ns
• @ 2.7V, 2.4MHz ==> 12.9ns
• @ 2.8V, 2.5MHz ==> 12.5ns
• @ 3.3V, 2.9MHz ==> 10.7ns

As expected, a serial 16-bit FET carry chain is much too slow. The incrementer result in the CPU will be fed directly to the synch RAM (when incrementing PC for example), so the setup time of 1.5ns applies here as well. Add to that the tpd for the source register, some transit time, clock skew, etc. and we're pretty much left with about 6.5ns for the incrementer (just like with the adder).

So, the next step was to try carry lookahead. Four levels of AND gates on this board simulate carry lookahead for the first 12 bits of the incrementer. In the test circuit, the lookahead carry is then fed to four FET switches to simulate incrementing the final four bits. In this case, we don't have to include the switch time in the circuit since that happens concurrently with the carry lookahead.

So, I configured the board accordingly (as above, except that R13 is moved to R12 and R15 is moved to R14) and ran the test. Here are the results:

• @ 2.5V, 4.9MHz ==> 6.4ns
• @ 2.7V, 5.2MHz ==> 6.0ns
• @ 2.8V, 5.4MHz ==> 5.8ns
• @ 3.3V, 5.9MHz ==> 5.3ns

All good results! -- so we now know we can make a 16-bit incrementer that will be fast enough.

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P.S. The four carry lookahead AND gates are on a single VQFN 74AUC08 IC. So, yes, soldering the VQFN package worked out just fine! That’s going to come in handy when it’s time to do layout.